The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device which may be operated at both high speed and low electric power.
In order to improve the performance of semiconductor integrated circuit devices composed of CMOS circuits, some methods have been proposed such as shrinkage of MOS transistors that are a components of the CMOS circuitry, lowering of absolute values of threshold voltages of the MOS transistors, and raising of a supply voltage. In actuality, however, with improvement of an operating speed of the CMOS circuit, the power consumption is increased accordingly. For example, as the threshold voltage of the MOS transistor is made lower and lower, the operating speed becomes higher and higher, but the leak current is also increased. Likewise, with enhancement of the supply voltage, the operating speed is improved but the operation power is increased as well. The increase of the power consumption gives rise to disadvantages of degrading the circuit performance and bringing about an erroneous operation. The heat caused by the increase of the power consumption has the adverse effect on the mount of the semiconductor integrated circuit device, which disadvantageously leads to enhancing the manufacturing cost. Therefore, faster operation and lower power consumption have been significant issues to improving the performance of the CMOS circuit.
As a method of overcoming these disadvantages, for example, reference may be made to the technique disclosed in 2000 International Solid-State Circuits Conference Digest of Technical Papers, pp. 294-295 (February, 2000). This technique is arranged so that a processor that is operated at high speed and low electric power may be realized by controlling the operating clock frequency and the supply voltage of a microprocessor composed of a CMOS circuit. If fast operation is required, by enhancing the clock frequency and the supply voltage, the operating speed may be improved while making the power consumption larger. On the other hand, if slow operation is allowed, by lowering the clock frequency and the supply voltage, the power consumption may be reduced. The combinational adjustment of these controls through the operating system realizes the fast operation and the low power consumption of the microprocessor.
In order to realize the semiconductor integrated circuit device composed of a CMOS circuit such as a microprocessor that is operated at high speed and low electric power, the foregoing technique of controlling the operating clock frequency and the supply voltage of the CMOS circuit is an effective means. This technique makes it possible to speed up the clock frequency and enhance the supply voltage when the microprocessor operates at high speed and on the contrary to lower the clock frequency and the supply voltage when it operates at low electric power or low speed, thereby improving the performance of the microprocessor.
In recent days, the MOS transistor is shrunken more and more. As a result, the dimensions and performances of the transistors in the manufacturing process are made greatly variable. FIG. 3 shows dependency of a supply voltage on an operating frequency of a CMOS circuit. In FIG. 3, an axis of abscissa denotes a supply voltage and an axis of ordinates denotes an operating frequency. As shown, mainly because of the variations in the performance of the transistor, the operating frequency of the CMOS circuit varies in the range of the highest (best) speed, the standard (typical) speed and the low (worst) speed at the same supply voltage. If the CMOS circuit having such variations in an operating speed is used for composing the semiconductor integrated circuit device such as a microprocessor, the operating speed guaranteed to the device is determined to be the worst speed. As shown, as the supply voltage is made lower, the operation of the CMOS circuit is made slower accordingly. In the worst speed, the degrade of the operating speed is quite conspicuous, which is an obstacle to the performance of the microprocessor.
The possible suppression of the variations in the operating characteristic in the CMOS circuit leads to guaranteeing the typical speed as shown in FIG. 3. This results in making the CMOS circuit far faster in operation and lower in power consumption. The variations can be realized by controlling the substrate bias of the MOS transistor.
It is a first object of the present invention to provide a semiconductor integrated circuit device which is arranged to suppress the characteristic variations of the CMOS circuit and thereby to improve the circuit performance.
It is a second object of the present invention to provide a semiconductor integrated circuit device which may be operated at low electric power and is suitable especially to a portable instrument operated by a built-in battery without degrading the operating speed.
It is a third object of the present invention to provide a semiconductor integrated circuit device which may be operated at high speed without having to increase the power consumption.
It is a fourth object of the present invention to provide a system having the above-mentioned semiconductor integrated circuit mounted thereon which may be battery-operated for a longer length of time.